In many integrated circuit (IC) applications, and in particular in safety critical applications, self-testing is an essential component of an IC device, whereby one or more self-tests are executed within at least a part of the IC device. Self-testing within an IC device, for example such as a System on Chip (SoC) device or the like, is typically implemented using one or more forms of built-in self-test (BIST) mechanism(s). A Logic built-in self-test (or LBIST) is one form of BIST mechanism in which hardware is provided within an IC device allowing the IC device to test its own operation, as opposed to reliance on external automated test equipment. Other forms of BIST include, by way of example only, MBIST (a BIST optimized for testing internal memory) and software based BIST.
In order to achieve a finer granularity BIST result over specific areas in an SoC, it is known for the SoC and its self-tests to be separated into discrete areas, or ‘partitions’. FIG. 1 illustrates a simplified representation of such LBIST partitions for an integrated circuit device such as an SoC 100. In FIG. 1, the SoC 100 has been arranged into i+1 partitions 110, with each partition 110 relating to a distinct area of the SoC 100. These partitions 110 traverse through (functionally) separate self-tests in order to receive information about the operational integrity of the distinct SoC areas. Each self-test is designed to ‘exercise’ the relevant SoC area in a particular manner such that the combination of tests provides comprehensive test coverage of the relevant SoC area.
BIST mechanisms are a powerful technique for determining quickly whether an IC device or vast regions (e.g., partitions) of an IC device are functional or not. However, a problem with conventional BIST implementations is that they only provide information about the presence of defects inside individual partitions, and do not provide sufficient granularity to identify more precisely within which functional component of a partition a defect may reside. In order to ensure a high level of availability in today's IC devices it is essential to determine the exact defective functional component or components. Only by knowing that information can a system react (in either HW or SW) in a targeted way to solve the issue or at least get around it so the IC device becomes functional again.
A higher self-test partition granularity results in a major increase in design effort and die area, and thus is typically only tolerated in a very limited number of situations.